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Features
* Industry-standard Architecture
- Emulates Many 20-pin PALs(R) - Low-cost Easy-to-use Software Tools * High-speed Electrically-erasable Programmable Logic Devices - 10 ns Maximum Pin-to-pin Delay * Several Power Saving Options Device ATF16V8B ATF16V8BQ ATF16V8BQL ICC, Standby 50 mA 35 mA 5 mA ICC, Active 55 mA 40 mA 20 mA
* CMOS and TTL Compatible Inputs and Outputs *
- Input and I/O Pull-up Resistors Advanced Flash Technology - Reprogrammable - 100% Tested High-reliability CMOS Process - 20 Year Data Retention - 100 Erase/Write Cycles - 2,000V ESD Protection - 200 mA Latchup Immunity Commercial, and Industrial Temperature Ranges Dual-in-line and Surface Mount Packages in Standard Pinouts PCI-compliant Green Package Options (Pb/Halide-free/RoHS Compliant) Available
Highperformance EE PLD ATF16V8B ATF16V8BQ ATF16V8BQL
*
* * * *
1. Description
The ATF16V8B is a high-performance CMOS (electricallyerasable) programmable logic device (PLD) that utilizes Atmel's proven electrically-erasable Flash memory technology. All speed ranges are specified over the full 5V 10% range for industrial temperature ranges, and 5V 5% for commercial temperature ranges. Several low-power options allow selection of the best solution for various types of power-limited applications. Each of these options significantly reduces total system power and enhances system reliability. The ATF16V8Bs incorporate a superset of the generic architectures, which allows direct replacement of the 16R8 family and most 20-pin combinatorial PLDs. Eight outputs are each allocated eight product terms. Three different modes of operation, configured automatically with software, allow highly complex logic functions to be realized.
0364J-PLD-7/05
Figure 1-1.
Block Diagram
2. Pin Configurations
Table 2-1.
Pin Name CLK I I/O OE VCC
Pin Configurations (All Pinouts Top View)
Function Clock Logic Inputs Bi-directional Buffers Output Enable +5V Supply
Figure 2-1.
I/CLK I1 I2 I3 I4 I5 I6 I7 I8 GND
TSSOP
1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC I/O I/O I/O I/O I/O I/O I/O I/O I9/OE
Figure 2-2.
DIP/SOIC
I/CLK I1 I2 I3 I4 I5 I6 I7 I8 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC I/O I/O I/O I/O I/O I/O I/O I/O I9/OE
Figure 2-3.
PLCC
I2 I1 I/CLK VCC I/O 3 2 1 20 19 I8 GND I9/OE I/O I/O 9 10 11 12 13 I3 I4 I5 I6 I7 4 5 6 7 8 18 17 16 15 14 I/O I/O I/O I/O I/O
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3. Absolute Maximum Ratings*
Temperature Under Bias.................................-55oC to +125oC Storage Temperature ......................................-65oC to +150oC Voltage on Any Pin with Respect to Ground .......................................-2.0 V to +7.0 V(1) Voltage on Input Pins with Respect to Ground During Programming...................................-2.0 V to +14.0 V(1) Programming Voltage with Respect to Ground .....................................-2.0 V to +14.0 V(1) *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Note:
1. Minimum voltage is -0.6V DC, which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is VCC + 0.75V DC, which may overshoot to 7.0V for pulses of less than 20 ns.
4. DC and AC Operating Conditions
Commercial Operating Temperature (Ambient) VCC Power Supply 0 C - 70 C 5V 5%
o o
Industrial -40oC - 85oC 5V 10%
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4.1
DC Characteristics
Parameter Input or I/O Low Leakage Current Input or I/O High Leakage Current Condition 0 VIN VIL(Max) 3.5 VIN VCC Com. B-10 Ind. Power Supply Current, Standby VCC = Max, VIN = Max, Outputs Open B-15 B-15 BQ-10 BQL-15 BQL-15 B-10 Ind. Clocked Power Supply Current VCC = Max, Outputs Open, f = 15 MHz B-15 B-15 BQ-10 BQL-15 BQL-15 Com. Ind. Com. Com. Ind. 60 55 55 40 20 20 100 85 95 55 35 40 -130 -0.5 2.0 VIN = VIH or VIL, VCC = Min VIN = VIH or VIL, VCC = Min IOL = -24 mA Com., Ind. IOH = -4.0 mA 2.4 0.8 VCC+0.75 0.5 mA mA mA mA mA mA mA V V V V Com. Ind. Com. Com. Ind. Com. 55 50 50 35 5 5 60 95 75 80 55 10 15 90 mA mA mA mA mA mA mA 55 Min Typ -35 Max -100 10 85 Units A A mA
Symbol IIL IIH
ICC
ICC2
IOS(1) VIL VIH VOL VOH Note:
Output Short Circuit Current Input Low Voltage Input High Voltage Output High Voltage Output High Voltage
VOUT = 0.5 V
1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
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4.2 AC Waveforms(1)
Note:
1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V 3.0V, unless otherwise specified.
4.3
AC Characteristics(1)
-10 -15 Max 10 Min 3 Max 15 ns 6 2 7.5 0 12 6 68 74 83 3 2 2 1.5 10 10 10 10 3 2 2 1.5 7 2 12 0 16 8 45 50 62 15 15 15 15 8 10 ns ns ns ns ns ns MHz MHz MHz ns ns ns ns Units Parameter Input or Feedback to Non-Registered Output Clock to Feedback Clock to Output Input or Feedback Setup Time Hold Time Clock Period Clock Width External Feedback 1/(tS + tCO) 8 outputs switching Min 3
Symbol tPD tCF tCO tS tH tP tW
fMAX
Internal Feedback 1/(tS + tCF) No Feedback 1/(tP)
tEA tER tPZX tPXZ Note:
Input to Output Enable -- Product Term Input to Output Disable -- Product Term OE pin to Output Enable OE pin to Output Disable 1. See ordering information for valid part numbers and speed grades.
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4.4
4.4.1
Input Test Waveforms
Input Test Waveforms and Measurement Levels
tR, tF < 5 ns (10% to 90%) 4.4.2 Output Test Loads (Commercial)
CL includes Test fixture and Probe capacitance
4.5
Pin Capacitance
Table 4-1. Pin Capacitance (f = 1 MHz, T = 25C(1))
Typ CIN COUT Note: 5 6 Max 8 8 Units pF pF Conditions VIN = 0V VOUT = 0V
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
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4.6 Power-up Reset
The registers in the ATF16V8Bs are designed to reset during power-up. At a point delayed slightly from VCC crossing VRST, all registers will be reset to the low state. As a result, the registered output state will always be high on power-up. This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the uncertainty of how VCC actually rises in the system, the following conditions are required: 1. The VCC rise must be monotonic, 2. After reset occurs, all input and feedback setup times must be met before driving the clock pin high, and 3. The clock must remain stable during tPR. Figure 4-1. Power-up Reset Waveforms
Table 4-2.
Parameter tPR VRST
Power-up Reset Parameters
Description Power-up Reset Time Power-up Reset Voltage Typ 600 3.8 Max 1,000 4.5 Units ns V
4.7
Preload of Registered Outputs
The ATF16V8B's registers are provided with circuitry to allow loading of each register with either a high or a low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A JEDEC file with preload is generated when a source file with vectors is compiled. Once downloaded, the JEDEC file preload sequence will be done automatically by most of the approved programmers after the programming.
5. Security Fuse Usage
A single fuse is provided to prevent unauthorized copying of the ATF16V8B fuse patterns. Once programmed, fuse verify and preload are inhibited. However, the 64-bit User Signature remains accessible. The security fuse should be programmed last, as its effect is immediate.
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6. Electronic Signature Word
There are 64 bits of programmable memory that are always available to the user, even if the device is secured. These bits can be used for user-specific data.
7. Programming/Erasing
Programming/erasing is performed using standard PLD programmers. See CMOS PLD Programming Hardware and Software Support for information on software/programming.
8. Input and I/O Pull-ups
All ATF16V8B family members have internal input and I/O pull-up resistors. Therefore, whenever inputs or I/Os are not being driven externally, they will float to VCC. This ensures that all logic array inputs are at known states. These are relatively weak active pull-ups that can easily be overdriven by TTL-compatible drivers (see input and I/O diagrams below). Figure 8-1. Input Diagram
Figure 8-2.
I/O Diagram
9. Functional Logic Diagram Description
The Logic Option and Functional Diagrams describe the ATF16V8B architecture. Eight configurable macrocells can be configured as a registered output, combinatorial I/O, combinatorial output, or dedicated input. The ATF16V8B can be configured in one of three different modes. Each mode makes the ATF16V8B look like a different device. Most PLD compilers can choose the right mode automatically. The user can also force the selection by supplying the compiler with a mode selection. The determining factors would be the usage of register versus combinatorial outputs and dedicated outputs versus outputs with output enable control. The ATF16V8B universal architecture can be programmed to emulate many 20-pin PAL devices. These architectural subsets can be found in each of the configuration modes described
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in the following pages. The user can download the listed subset device JEDEC programming file to the PLD programmer, and the ATF16V8B can be configured to act like the chosen device. Check with your programmer manufacturer for this capability. Unused product terms are automatically disabled by the compiler to decrease power consumption. A security fuse, when programmed, protects the content of the ATF16V8B. Eight bytes (64 fuses) of User Signature are accessible to the user for purposes such as storing project name, part number, revision, or date. The User Signature is accessible regardless of the state of the security fuse.
10. Software Support
Atmel-WinCUPL is a free tool, available on Atmel's web site and can be used to design in all members of the Atmel ATF16V8B family of SPLDs. Table 10-1 lists popular compilers with the appropriate device mnemonics Table 10-1. Compiler Mode Selection
Registered ABEL, Atmel-ABEL CUPL, Atmel-WinCUPL LOG/iC OrCAD-PLD PLDesigner Tango-PLD Note: P16V8R G16V8MS GAL16V8_R(1) "Registered" P16V8R G16V8R Complex P16V8C G16V8MA GAL16V8_C7(1) "Complex" P16V8C G16V8C Simple P16V8AS G16V8AS GAL16V8_C8(1) "Simple" P16V8C G16V8AS Auto Select P16V8 G16V8 GAL16V8 GAL16V8A P16V8A G16V8
1. Only applicable for version 3.4 or lower.
11. Macrocell Configuration
Software compilers support the three different OMC modes as different device types. Most compilers have the ability to automatically select the device type, generally based on the register usage and output enable (OE) usage. Register usage on the device forces the software to choose the registered mode. All combinatorial outputs with OE controlled by the product term will force the software to choose the complex mode. The software will choose the simple mode only when all outputs are dedicated combinatorial without OE control. The different device types can be used to override the automatic device selection by the software. For further details, refer to the compiler software manuals. When using compiler software to configure the device, the user must pay special attention to the following restrictions in each mode. In registered mode pin 1 and pin 11 are permanently configured as clock and output enable, respectively. These pins cannot be configured as dedicated inputs in the registered mode. In complex mode pin 1 and pin 11 become dedicated inputs and use the feedback paths of pin 19 and pin 12 respectively. Because of this feedback path usage, pin 19 and pin 12 do not have the feedback option in this mode. In simple mode all feedback paths of the output pins are routed via the adjacent pins. In doing so, the two inner most pins (pins 15 and 16) will not have the feedback option as these pins are always configured as dedicated combinatorial output.
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11.1
ATF16V8B Registered Mode
PAL Device Emulation/PAL Replacement. The registered mode is used if one or more registers are required. Each macrocell can be configured as either a registered or combinatorial output or I/O, or as an input. For a registered output or I/O, the output is enabled by the OE pin, and the register is clocked by the CLK pin. Eight product terms are allocated to the sum term. For a combinatorial output or I/O, the output enable is controlled by a product term, and seven product terms are allocated to the sum term. When the macrocell is configured as an input, the output enable is permanently disabled. Any register usage will make the compiler select this mode. The following registered devices can be emulated using this mode: 16R8 16R6 16R4 16RP8 16RP6 16RP4
Figure 11-1. Registered Configuration for Registered Mode(1)(2)
Notes:
1. Pin 1 controls common CLK for the registered outputs. Pin 11 controls common OE for the registered outputs. Pin 1 and Pin 11 are permanently configured as CLK and OE. 2. The development software configures all the architecture control bits and checks for proper pin usage automatically.
Figure 11-2. Combinatorial Configuration for Registered Mode(1)(2)
Notes:
1. Pin 1 and Pin 11 are permanently configured as CLK and OE. 2. The development software configures all the architecture control bits and checks for proper pin usage automatically.
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Figure 11-3. Registered Mode Logic Diagram
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11.2
ATF16V8B Complex Mode
PAL Device Emulation/PAL Replacement. In the complex mode, combinatorial output and I/O functions are possible. Pins 1 and 11 are regular inputs to the array. Pins 13 through 18 have pin feedback paths back to the AND-array, which makes full I/O capability possible. Pins 12 and 19 (outermost macrocells) are outputs only. They do not have input capability. In this mode, each macrocell has seven product terms going to the sum term and one product term enabling the output. Combinatorial applications with an OE requirement will make the compiler select this mode. The following devices can be emulated using this mode: 16L8 16H8 16P8 Figure 11-4. Complex Mode Option
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Figure 11-5. Complex Mode Logic Diagram
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11.3
ATF16V8B Simple Mode
PAL Device Emulation/PAL Replacement. In the Simple Mode, 8 product terms are allocated to the sum term. Pins 15 and 16 (center macrocells) are permanently configured as combinatorial outputs. Other macrocells can be either inputs or combinatorial outputs with pin feedback to the AND-array. Pins 1 and 11 are regular inputs. The compiler selects this mode when all outputs are combinatorial without OE control. The following simple PALs can be emulated using this mode: 10L8 12L6 14L4 16L2 10H8 12H6 14H4 16H2 10P8 12P6 14P4 16P2
Figure 11-6. Simple Mode Option
Note:
* Pins 15 and 16 are always enabled.
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Figure 11-7. Simple Mode Logic Diagram
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12. Test Characterization Data
SUPPLY CURRENT vs. INPUT FREQUENCY
ATF16V8B/BQ (VCC = 5V, TA = 25C)
75
SUPPLY CURRENT vs. INPUT FREQUENCY
ATF16V8BL/BQL (VCC = 5V, TA = 25C)
75
ATF16V8B I C C m A
50
ATF16V8B I C C m A
50
ATF16V8BQL
25
ATF16V8BQ
25
0 0 20 40 60 80 100
0 0 25 50 75 100
FREQUENCY (MHz)
FREQUENCY (MHz)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
65
ATF16V8B/BQ (TA = 25C) ATF16V8B
I C C m A
55
45
ATF16V8BQ
35
25 4.50
4.75
5.00
5.25
5.50
SUPPLY VOLTAGE (V)
OUTPUT SOURCE CURRENT
-10 -12
vs. SUPPLY VOLTAGE (TA = 25C)
I O H m A
-14 -16 -18 -20 -22 -24 4.5
4.7
4.9
5.1
5.3
5.5
SUPPLY VOLTAGE (V)
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NORMALIZED TPD
vs. SUPPLY VOLTAGE (TA=25C)
1.3
N O R M T P D
1.15 ATF16V8B/BQ 1 ATF16V8BQL 0.85
0.7
4.50 4.75 5.00 5.25 5.50
SUPPLY VOLTAGE (V)
NORMALIZED TCO
vs. SUPPLY VOLTAGE(TA=25C)
1.3 N O R M T C O 0.7
4.50 4.75 5.00 5.25 5.50
1.15
ATF16V8B/BQ
1 ATF16V8BQL 0.85
SUPPLY VOLT AGE (V)
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13. ATF16V8B Ordering Information
13.1
tPD (ns)
ATF16V8B Standard Package Options
tS (ns) tCO (ns) Ordering Code ATF16V8B-10JC ATF16V8B-10PC ATF16V8B-10SC ATF16V8B-10XC ATF16V8B-10JI ATF16V8B-10PI ATF16V8B-10SI ATF16V8B-10XI ATF16V8B-15JC ATF16V8B-15PC ATF16V8B-15SC ATF16V8B-15XC Package 20J 20P3 20S 20X 20J 20P3 20S 20X 20J 20P3 20S 20X 20J 20P3 20S 20X Operation Range
Commercial (0C to 70C)
10
7.5
7
Industrial (-40C to 85C)
Commercial (0C to 70C)
15
12
10 ATF16V8B-15JI ATF16V8B-15PI ATF16V8B-15SI ATF16V8B-15XI Industrial (-40C to 85C)
Note:
The last time buy date is Sept. 30, 2005 for shaded parts.
13.2
tPD (ns) 10
ATF16V8B Green Package Options (Pb/Halide-free/RoHS Compliant)
tS (ns) 7.5 tCO (ns) 7 Ordering Code ATF16V8B-10JU ATF16V8B-15JU ATF16V8B-15PU ATF16V8B-15SU ATF16V8B-15XU Package 20J 20J 20P3 20S 20X Industrial (-40C to 85C) Operation Range
15
12
10
13.3
Using "C" Product for Industrial
To use commercial product for Industrial temperature ranges, down-grade one speed grade from the "I" to the "C" device (7 ns "C" = 10 ns "I") and de-rate power by 30%.
Package Type
20J 20P3 20S 20X
20-lead, Plastic J-leaded Chip Carrier (PLCC) 20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 20-lead, 0.300" Wide, Plastic Gull-wing Small Outline (SOIC) 20-lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline (TSSOP)
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14. ATF16V8BQ/BQL Ordering Information
14.1
tPD (ns)
ATF16V8BQ and ATF16V8BQL Ordering Information
tS (ns) tCO (ns) Ordering Code ATF16V8BQ-10JC Package 20J 20P3 20S 20X 20J 20P3 20S 20X 20J 20P3 20S 20X Operation Range
10
7.5
7
ATF16V8BQ-10PC ATF16V8BQ-10SC ATF16V8BQ-10XC ATF16V8BQL-15JC ATF16V8BQL-15PC ATF16V8BQL-15SC ATF16V8BQL-15XC ATF16V8BQL-15JI ATF16V8BQL-15PI ATF16V8BQL-15SI ATF16V8BQL-15XI
Commercial (0C to 70C)
15
12
10
Commercial (0C to 70C)
Industrial (-40C to 85C)
Note:
The last time buy date is Sept. 30, 2005 for shaded parts.
14.2
tPD (ns)
ATF16V8BQ and ATF16V8BQL Green Package Options (Pb/Halide-free/RoHS Compliant)
tS (ns) tCO (ns) Ordering Code ATF16V8BQL-15JU ATF16V8BQL-15PU ATF16V8BQL-15SU ATF16V8BQL-15XU Package 20J 20P3 20S 20X Operation Range Industrial (-40C to 85C)
15
12
10
14.3
Using "C" Product for Industrial
To use commercial product for Industrial temperature ranges, down-grade one speed grade from the "I" to the "C" device (7 ns "C" = 10 ns "I") and de-rate power by 30%.
Package Type 20J 20P3 20S 20X 20-lead, Plastic J-leaded Chip Carrier (PLCC) 20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 20-lead, 0.300" Wide, Plastic Gull-Wing Small Outline (SOIC) 20-lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline (TSSOP)
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15. Packaging Information
15.1 20J - PLCC
1.14(0.045) X 45
PIN NO. 1 IDENTIFIER
1.14(0.045) X 45
0.318(0.0125) 0.191(0.0075)
e E1 B E B1 D2/E2
D1 D A
A2 A1
0.51(0.020)MAX 45 MAX (3X)
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E Notes: 1. This package conforms to JEDEC reference MS-018, Variation AA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. E1 D2/E2 B B1 e MIN 4.191 2.286 0.508 9.779 8.890 9.779 8.890 7.366 0.660 0.330 NOM - - - - - - - - - - 1.270 TYP MAX 4.572 3.048 - 10.033 9.042 10.033 9.042 8.382 0.813 0.533 Note 2 Note 2 NOTE
10/04/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 20J, 20-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO. 20J REV. B
R
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15.2
20P3 - PDIP
D
PIN 1
E1
A
SEATING PLANE
L B1 e E B
A1
C eC eB
SYMBOL A A1 D E E1 B Notes: 1. This package conforms to JEDEC reference MS-001, Variation AD. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). B1 L C eB eC e
COMMON DIMENSIONS (Unit of Measure = mm) MIN - 0.381 24.892 7.620 6.096 0.356 1.270 2.921 0.203 - 0.000 NOM - - - - - - - - - - - MAX 5.334 - 26.924 8.255 7.112 0.559 1.551 3.810 0.356 10.922 1.524 Note 2 Note 2 NOTE
2.540 TYP
1/23/04 2325 Orchard Parkway San Jose, CA 95131 TITLE 20P3, 20-lead (0.300"/7.62 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO. 20P3 REV. D
R
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15.3 20S - SOIC
Dimensions in Millimeters and (Inches). Controlling dimension: Inches. JEDEC Standard MS-013
0.51(0.020) 0.33(0.013)
7.60 (0.2992) 10.65 (0.419) 7.40 (0.2914) 10.00 (0.394) PIN 1 ID
PIN 1
1.27 (0.050) BSC
13.00 (0.5118) 12.60 (0.4961)
2.65 (0.1043) 2.35 (0.0926)
0.30(0.0118) 0.10 (0.0040)
0 ~ 8
0.32 (0.0125) 0.23 (0.0091)
1.27 (0.050) 0.40 (0.016)
10/23/03 2325 Orchard Parkway San Jose, CA 95131 TITLE 20S, 20-lead, 0.300" Body, Plastic Gull Wing Small Outline (SOIC) DRAWING NO. 20S REV. B
R
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15.4
20X - TSSOP
Dimensions in Millimeters and (Inches). Controlling dimension: Millimeters. JEDEC Standard MO-153 AC
INDEX MARK
PIN 1
4.50 (0.177) 6.50 (0.256) 4.30 (0.169) 6.25 (0.246)
6.60 (.260) 6.40 (.252)
1.20 (0.047) MAX
0.65 (.0256) BSC 0.30 (0.012) 0.19 (0.007)
0.15 (0.006) 0.05 (0.002)
SEATING PLANE
0 ~ 8
0.20 (0.008) 0.09 (0.004)
0.75 (0.030) 0.45 (0.018)
10/23/03 2325 Orchard Parkway San Jose, CA 95131 TITLE 20X, (Formerly 20T), 20-lead, 4.4 mm Body Width, Plastic Thin Shrink Small Outline Package (TSSOP) DRAWING NO. 20X REV. C
R
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16. Revision History
16.1 0364J
1. ATF16V8B-25 JC/PC/SC/XC/JI/PI/SI/XI were obseleted in August 1999 ATF16V8BQL-25 JC/PC/SC/XC/JI/PI/SI/XI were obseleted in August 1999 These devices were removed from Section 13. "ATF16V8B Ordering Information" on page 19 and Section 14. "ATF16V8BQ/BQL Ordering Information" on page 20. 2. Green Package options added in 2005.
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Atmel Corporation
2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
Atmel Operations
Memory
2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314
RF/Automotive
Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759
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